1. Field of the Invention
The present invention relates generally to a filter circuit utilizing a charge transfer device such as a bucket brigade device or a charge coupled device, and is directed more particularly to a non-recursive transversal filter.
2. Description of the Prior Art
In general, a prior art filter circuit using a bucket brigade device may be as shown in FIG. 1. In simplest terms, a bucket brigade device periodically stores an input analog or digital signal from an input terminal 1 in a capacitor C0, then passes the stored charge a step at a time from left to right through capacitors C1, C2, . . . . At each step, a new input signal value is stored in C0. Thus, a moving stream of stored charges are moved along the bucket brigade device.
Input terminal 1 applies a signal voltage V.sub.S to the base of a PNP transistor 2 whose collector is grounded and whose emitter is connected through a resistor 3 to a power supply terminal maintained at a supply voltage +V.sub.CC and also through the cathode terminal of a diode 5 to a hot side of capacitor C0. The other or cold side of capacitor C.sub.0 is connected to a clock terminal 6. The hot side of capacitor C0 is also connected to the emitter of an NPN transistor Q1 whose collector is connected to the emitter of an NPN transistor Q2 of the next stage. Similarly, the collectors and emitters of NPN transistors Q2, Q3, . . . are connected together, and capacitors C1, C2, . . . are connected between the bases and collectors of the respective transistors Q1, Q2, . . . , respectively. The capacitance of capacitors C0, C1, C2, . . . are all equal to the same capacitance value C. The bases of odd numbered transistors Q1, Q3, . . . are connected through a clock terminal 7 to a clock driver 8. The bases of even numbered transistors Q2, Q4, . . . are connected through clock terminal 6 to clock driver 8, respectively.
Clock terminals 6 and 7 are supplied with clock signals .phi.1 and .phi.2 (FIGS. 2A and 2B respectively) which have potentials or levels V.sub.DC and V.sub.DC +V.sub.P, at a 50% duty cycle. Clock signals .phi.1 and .phi.2 are 180.degree. out of phase. The voltage V.sub.P satisfies condition (1) with respect to supply voltage V.sub.CC at power supply terminal 4. EQU V.sub.CC &gt;V.sub.DC +2V.sub.P ( 1)
Further, signal voltage V.sub.S at input terminal 1 satisfies condition (2). EQU V.sub.DC +V.sub.P .ltoreq.V.sub.s .ltoreq.V.sub.DC +2V.sub.P ( 2)
The voltage V.sub.DC applied to the bases of transistors Q1, Q2, Q3, . . . is insufficient to turn them on but the voltage V.sub.DC +V.sub.P is sufficient to bias them into their active regions.
As an initial condition, assume that all capacitors are charged to voltage V.sub.P and that signal voltage V.sub.S applied to input terminal 1 is a first DC value V.sub.S1. Signal voltage V.sub.S1 is thus applied to the cathode of diode 5. At time t.sub.o (FIG. 2A), the clock signal .phi.1 changes to V.sub.DC +V.sub.P and clock signal 2 changes to V.sub.DC. The voltage V.sub.DC at the base of transistor Q1 cuts off this transmission. The voltage V.sub.DC +V.sub.P at the upper or cold side of capacitor C.sub.o produces a voltage of V.sub.DC +2V.sub.P (FIG. 2C) at the lower or hot side of capacitor C0. According to equation (2), this voltage at the hot side of capacitor C0 and at the anode of diode 5 exceeds the signal voltage V.sub.S1 at the cathode of diode 5. Thus the charge in capacitor C0 bleeds off through diode 5 until the voltage at the hot side of capacitor C0 equals the signal voltage V.sub.S1. The charge remaining in capacitor C0 at this time is {V.sub.S1 -(V.sub.DC +V.sub.P)}C.
At time t.sub.1 (FIG. 2A), clock signal .phi..sub.1 decreases to voltage V.sub.DC. The voltage at the hot side of capacitor C0 is changed to V.sub.S1 -V.sub.P (FIG. 2C). At the same time, clock signal .phi..sub.2 (FIG. 2B) is increased to voltage V.sub.DC +V.sub.P. This voltage, applied to the base of transistor Q1, biases transistor Q1 into its active region. The same voltage applied to the cold side of capacitor C1 produces a voltage V.sub.DC +2V.sub.P (FIG. 2D) at the hot side of capacitor C1. Transistor Q2 is cut off by clock signal .phi.1 at its base. An amount of charge is fed from capacitor C1 through the collector-emitter path of transistor Q1 to increase the voltage at the hot side of capacitor C0 to V.sub.DC +V.sub.P. This occurs due to the voltage V.sub.DC +V.sub.P at the base of transistor Q1. Since the voltage at the hot side of capacitor C0 changes from V.sub.S1 -V.sub.P to V.sub.DC +V.sub.P, the charge transferred from the hot side of capacitor C1 to the hot side of capacitor C0 is expressed by equation (3). ##EQU1##
Since a charge of V.sub.P .multidot.C was initially stored in the capacitor C1, its final charge is given as follows: ##EQU2## That is, during the period t.sub.o to t.sub.1, a voltage is stored in capacitor C0 which is equal to V.sub.S1 -(V.sub.DC +V.sub.P). This voltage is transferred to capacitor C1 during the period t.sub.1 to t.sub.2 so that the voltage on capacitor C0 returns to V.sub.DC +V.sub.P. Since transistor Q2 is OFF at this time, capacitors C2, C3, . . . are not affected.
Further, during period t.sub.2 to t.sub.3, signal voltage V.sub.S may assume a value V.sub.S2. Capacitor C0 is charged to V.sub.S2 -(V.sub.DC +V.sub.P) while capacitor C1 is returned to V.sub.DC +V.sub.P by this voltage at the base of transistor Q2. By the process previously described, capacitor C2 is charged to V.sub.S1 -(V.sub.DC +V.sub.P). Since the transistor Q3 is OFF, capacitors C3, . . . are not affected. The above operation is repeated and the signal is transferred from left to right on FIG. 1 in synchronism with clock signals .phi.1 and .phi.2.
When a transversal filter of, for example, a non-recursive type is formed using the above bucket brigade device, a plurality of intermediate taps are provided at appropriate points in the sequence. This has the effect of providing signals with different delay times which may be weighted in a predetermined way and added successively to produce an output signal.
The hot sides of capacitors C0, C2 and C4, from which signals are derived, are connected to the bases of emitter follower transistors 91, 92 and 93, respectively. The emitters of the transistors 91, 92 and 93 are connected to input terminals of differential amplifiers 94, 95 and 96, respectively. The other input terminals of differential amplifiers 94, 95 and 96 are connected to a constant voltage source represented by a battery. Outputs of differential amplifiers 94, 95 and 96 are commonly connected through an emitter follower transistor 98 to an output terminal 10.
The signals from the intermediate taps are delivered through emitter follower transistors 91, 92 and 93 and added in an analog manner in differential amplifiers 94, 95 and 96. The voltages may be weighted by adjusting the gains of the differential amplifiers to desired values.
Analog adding by differential amplifiers, as in the prior art, requires an excessive number of components with a resultant high power dissipation. Also, slight imbalance in the gain adjustment of the differential amplifiers may upset the balance of the circuit and produce scattering in the DC level. As a consequence, the correct relationships between input and output may not be achieved or the output DC level may become unstable.
Further, due to the presence of the collector-base capacitance C.sub.CB of emitter follower transistors 91, 92 and 93, the effective pulse height of the clocking signal is reduced by a factor of C/(C+C.sub.CB) and the dynamic range of the signal is proportionately lowered. Also, the signal is affected by the base current of emitter follower transistors 91, 92 and 93. Therefore, a non-recursive transversal filter utilizing the circuit shown in FIG. 1 is not satisfactory.